The Acceleration of Everything

The concept of the acceleration of everything has fascinated me since I became Nortel’s Chief Procurement Officer many years ago.

Prior to that position, I had worked in semiconductor technology development and Operations and had spent some time in China negotiating and running joint venture companies.

I was aware of Moore’s law and the enabling power of silicon technology and software but it was not until I was given the mandate, as CPO, to accelerate time to market by using suppliers differently that the enormity and consequence of the acceleration of everything really hit me.

The acceleration of everything has been going on for some time; in fact, it started with the Big Bang. For those of you whose memories don’t go back quite that far, I suggest you watch the TED talk titled “The accelerating power of technology” by Ray Kurzweil. Don’t worry about it being a talk from 2005 as it covers about 14 billion years. What you will see is that the pace of change has been accelerating since the beginning. Adoption times have been getting shorter and shorter and this acceleration continues at a non-linear pace.

This may not be news to you.

What may be new are the implications that this has on you and how your company works. It shouts High Risk to those who do not innovate and to those stuck in old ways of working, too encumbered with tried and true paradigms.

I credit Michael E. Porter of Harvard University with this next concept although I may be incorrect. What I am not incorrect about is it importance. Picture a graph plotted on linear paper where the Y-axis is the rate of change increasing upward and the X-axis is time moving to the right. The plot of the acceleration of everything is a curve starting at (0, 0) and moving upwards at an accelerated rate as time progresses.

Assume you are on this curve, just to the right of the (0, 0) point, and that your competitor does something exceptional. You need to react to catch up. Draw an arrow horizontal to the X-axis to represent how long your business process will take to do so. From the tip of that arrow, draw a vertical arrow that reaches up to touch the curve. This vertical arrow represents the amount of hustle that you must muster to stay in the game.

Now assume that time has passed and another competitor does something disruptive but that you are using the same business practices.

Redraw this scenario and you will see that your amount of hustle has increased. If you go far enough to the right, you will never catch up. Now place the amount of hustle that was required in the first example on the new time line and position it so that it touches the time line and the curve.

This shows you how much time you have for your business process to work. It’s no wonder that so many companies fail!

If you are lost plotting the diagram, I have included one for you below.

Rate of Change v2

My move from technology to purchasing gives me a unique perspective on how electronic designers can influence the supply chain to accelerate time to market and time to costs. I am writing about this subject in a book titled “Supply Chain Fundamentals: A Guide for Electronic Designers and Supply Chain Professionals.” I would like your help in writing it by getting your feedback on the subject and content.

A draft of the Table of Contents and Chapter 1 are currently available on Lytica’s website. You can download these drafts for review and provide feedback through the comments section on each content page. I want this book to be comprehensive, readable and useful to anyone in our industry.

Let me give you one example of how electronic designers could have a significant supply chain impact by taking a final, usually ignored, step.

ASICs combined with software was a powerful evolutionary step in electronics. ASICs brought incredible functionality at low cost to electronic products but often came with a prohibitive cost in NRE charges (>$ 1M / Design Cycle).

This high cost drove innovation in design technology to the point that now ASIC devices are universally right the first time. It also drove lower-cost alternatives; first as Gate Arrays, then as Custom Programmable Logic Devices (CPLDs) and, finally, as FPGAs for field programmable gate array. The FPGA replaces the high ASIC NRE charge with a low engineering cost but raises the price per part significantly when compared to an ASIC.

Another FPGA benefit is that the design specification doesn’t have to be completely known in order to create a prototype. If you get the design wrong, it can easily and quickly be reprogrammed until it works. The FPGA manufacturers have developed outstanding time to market enabling technology.

If your product is high volume, the FPGA prove-in followed by an ASIC conversion is a cost effective route. If the volume is moderate to low the FPGA, along with its higher cost, usually stays in the product forever. There are solutions that designers could use to prevent this high lifecycle cost but they are usually not acted on. The solutions come from the FPGA vendors themselves. I will describe the one from Xilinx although others offer solutions as well.

EasyPath is a Xilinx product that gives you the same FPGA component at a price between that of the ASIC and the FPGA. Xilinx will load and test your bit map on the FPGA. They will only test the device for the functionality and transistors that are used thereby greatly reducing their testing cost and increasing their yield. This delivers immediate cost reduction to anyone with sub-ASIC volume FPGA needs.

As an electronic designer, you should do either of the following to aid in Time-to-Cost acceleration if you use mid volume FPGAs:

1. Plan a design cycle in the R&D program for an EasyPath-like implementation once the FPGA code is stable. Verification costs should be near zero because it’s the same device with the same program, or

2. If you missed point 1, document the design so the others will know which design file goes with your bit map so that an EasyPath-like cost reduction can be entertained. It is amazing how many FPGAs are in production without known, good design files.

These steps will pay significant dividends to your company and remember, in nature, the fast usually eat the slow.

By Ken Bradley – Lytica Inc. Founder/Chairman/CTO

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Ken Bradley

Ken Bradley is the Chairman/CTO & founder of Lytica Inc., the world’s only provider of electronic component spend analytics and risk intelligence using real customer data.

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